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4533f?blurf?09/04 features single 3-v supply voltage high power-added efficient power amplifier (p out typically 23 dbm) ramp-controlled output power low-noise preamplifier (nf typically 2.1 db) biasing for external pin diode t/r switch current-saving standby mode few external components packages: ? psso20 ? qfn20 with extended performance electrostatic sensitive device. observe precautions for handling. description the t7024 is a monolithic sige transmit/receive front-end ic with power amplifier, low-noise amplifier and t/r switch driver. it is especially designed for operation in tdma systems like bluetooth ? and wdct. due to the ramp-control feature and a very low quiescent current, an external switch transistor for v s is not required. figure 1. block diagram pa pa_in v3_pa_out ramp v2_pa v1_pa lna lna_out lna_in tx/rx/ standby control pu rx_on vs_lna switch_out r_switch tx rx bluetooth ? /ism 2.4-ghz front- end ic t7024
2 t7024 4533f?blurf?09/04 pin configuration figure 2. pinning psso20 figure 3. pinning qfn20 1 2 3 4 5 6 7 8 10 9 19 18 17 16 14 15 13 12 11 20 lna_in vs_lna gnd v3_pa_out v3_pa_out v3_pa_out switch_out gnd gnd pa_in v1_pa gnd v2_pa v2_pa rx_on lna_out gnd ramp r_switch pu t7024 1 2 3 4 5 15 14 13 12 11 10 6 7 8 9 16 20 19 18 17 lna_out rx_on pu r_switch switch_out g n d v s _ l n a g n d l n a _ i n g n d v3_pa_out v3_pa_out v3_pa_out gnd ramp v 2 _ p a v 2 _ p a g n d v 1 _ p a p a _ i n t7024 pin description pins psso20 pins qfn20 symbol function 1 4 r_switch resistor to gnd sets the pin diode current 2 5 switch_out switched current output for pin diode 36gndground 4 7 lna_in low-noise amplifier input 5 9 vs_lna supply voltage input for low-noise amplifier 68gndground 7 11 v3_pa_out inductor to power supply and matching network for power amplifier output 8 12 v3_pa_out inductor to power supply and matching network for power amplifier output 9 13 v3_pa_out inductor to power supply and matching network for power amplifier output 10 10 gnd ground 11 15 ramp power ramping control input 12 16 v2_pa inductor to power supply for power amplifier 13 17 v2_pa inductor to power supply for power amplifier 14 14 gnd ground 15 19 v1_pa supply voltage for power amplifier 16 20 pa_in power amplifier input 17 18 gnd ground 18 1 lna_out low-noise amplifier output 19 2 rx_on rx active high 20 3 pu power-up active high slug slug gnd ground
3 t7024 4533f?blurf?09/04 handling do not operate this part near strong electrostatic fields. this ic meets class 1 esd test requirement (hbm in accordance to eia/jesd22-a114-a (october 97) and class a esd test requirement (mm) in accordance to eia/jesd22-a115a. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters symbol value unit supply voltage pins vs_lna, v1_pa, v2_pa, v3_pa_out v s 6v junction temperature t j 150 c storage temperature t stg -40 to +125 c rf input power lna p inlna 5dbm rf input power pa p inpa 10 dbm thermal resistance parameters symbol value unit junction ambient pssop20, slug soldered on pcb r thja 19 k/w junction ambient qfn20, slug soldered on pcb r thja 27 k/w operating range all voltages are referred to ground (pins gnd and slug). power supply points are vs_lna, v1_pa, v2_pa, v3_pa_out. the table represents the sum of all supply currents depending on the tx/rx mode. parameters symbol min. typ. max. unit supply voltage pins v1_pa, v2_pa and v3_pa_out v s 2.7 3.0 4.6 v supply voltage, pin vs_lna v s 2.7 3.0 5.5 v supply current tx, psso20 qfn20 supply current rx i s i s i s 190 165 8 ma ma ma standby current, pu = 0 i s_standby 10 a ambient temperature t amb -25 +25 +85 c
4 t7024 4533f?blurf?09/04 electrical characteristics test conditions (unless otherwise specified): v s = 3.0 v, t amb = 25c parameters test conditions symbol min. typ. max. unit power amplifier (1) supply voltage pins v1_pa, v2_pa, v3_pa_out v s 2.7 3.0 4.6 v supply current tx psso20 tx qfn20 i s_tx i s_tx 190 165 ma ma rx (pa off), v ramp 0.1 v i s_rx 10 a standby current standby i s_standby 10 a frequency range tx f 2.4 2.5 ghz gain-control range tx ? gp 60 42 db power gain maximum tx, pin pa_in to v3_pa_out gp 28 30 33 db power gain minimum tx, pin pa_in to v3_pa_out gp -40 -17 db ramping voltage maximum tx, power gain (maximum) pin ramp v ramp max 1.7 1.75 1.83 v ramping voltage minimum tx, power gain (minimum) pin ramp v ramp min 0.1 v ramping current maximum tx, v ramp = 1.75 v, pin ramp i ramp max 0.5 ma power-added efficiency tx psso20 tx qfn20 pa e pa e 30 35 35 40 % % saturated output power tx, input power = 0 dbm referred to pins v3_pa_out p sat 22 23 24 dbm input matching (2) tx, pin pa_in load vswr < 1.5:1 output matching (2) tx, pins v3_pa_out load vswr < 1.5:1 harmonics at p sat = 23 dbm tx, pins v3_pa_out 2 fo -30 dbc tx, pins v3_pa_out 3 fo -30 dbc t/r switch driver (current programming by external resistor from r_switch to gnd) switch-out current output standby, pin switch_out i s_o_standby 1 a rx i s_o_rx 1 a tx at 100 ? i s_o_100 1.7 ma tx at 1.2 k ? i s_o_1k2 7 ma tx at 33 k ? i s_o_33k 17 ma tx at i s_o_r 19 ma low-noise amplifier (3) supply voltage all, pin vs_lna v s 2.7 3.0 5.5 v supply current rx i s 8 9 ma notes: 1. power amplifier shall be unconditionally stable, maximum duty cycle 100%, true cw operation, maximum load mismatch and duration: load vswr = 10:1 (all phases) 10 s, z g = 50 ? . 2. with external matching network, load impedance 50 ? . 3. low-noise amplifier shall be unconditionally stable. 4. with external matching components. 5. lna gain can be adjusted with rx_on voltage according to figure 19 on page 11. please note, that for rx_on below 1.4 v the t/r switch driver switches to tx mode.
5 t7024 4533f?blurf?09/04 supply current (lna and control logic) tx (control logic active) pin vs_lna i s 0.5 ma standby current standby, pin vs_lna i s_standby 1 10 a frequency range rx f 2.4 2.5 ghz power gain (5) rx, pin lna_in to lna_out gp 15 16 19 db noise figure rx psso20 rx qfn20 nf nf 2.5 2.1 2.8 2.3 db db gain compression rx, referred to pin lna_out o1db -9 -7 -6 dbm 3 rd -order input interception point rx iip3 -16 -14 -13 dbm input matching (4) rx, pin lna_in vswrin 2:1 output matching (4) rx, pin lna_out vswrout 2:1 logic input levels (rx_on, pu) (5) high input level = ?1? pins rx_on and pu v ih 2.4 v s, lna v low input level = ?0? v il 0 0.5 v high input current = ?1? v ih = 2.4 v i ih 40 60 a low input current = ?0? i il 0.2 a electrical characteristics (continued) test conditions (unless otherwise specified): v s = 3.0 v, t amb = 25c parameters test conditions symbol min. typ. max. unit notes: 1. power amplifier shall be unconditionally stable, maximum duty cycle 100%, true cw operation, maximum load mismatch and duration: load vswr = 10:1 (all phases) 10 s, z g = 50 ? . 2. with external matching network, load impedance 50 ? . 3. low-noise amplifier shall be unconditionally stable. 4. with external matching components. 5. lna gain can be adjusted with rx_on voltage according to figure 19 on page 11. please note, that for rx_on below 1.4 v the t/r switch driver switches to tx mode. control logic pa and lna/antenna switch driver pu rx_on ramp (1) pa lna antenna switch driver operation mode 0 0 0 off off off standby 001onoff off (2) 010offon off (3) 0 1 1 on on off (4) 1 0 0 off off on (4) 101onoff on tx 110offon off rx 1 1 1 on on off (5) notes: 1. ?0? = v ramp 0.1 v, ?1? = v ramp typically 1.75 v, 1.3 v < v ramp < 1.83 v controls gain and output power, compare figure 9 on page 7 and figure 13 on page 9 2. only for special operation, e.g. only pa operation, no lna/switch driver operation 3. only for special operation, e.g. no switch driver operation 4. only for special operation 5. only for special operation, e.g. separate tx/rx antennas, tx and rx operation at the same time
6 t7024 4533f?blurf?09/04 typical operating characteristics figure 4. lna (psso20): gain and noise figure versus frequency figure 5. lna (n20): gain and noise figure versus frequency figure 6. lna: nf and gain versus temperature 0 5 10 15 20 2000 2200 2400 2600 2800 3000 frequency (mhz) gain (db) 0 1 2 3 4 5 6 7 8 nf (db) nf gain 0 5 10 15 20 25 2000 2200 2400 2600 2800 3000 frequency (mhz) gain (db) 0 1 2 3 4 5 nf (db) nf gain -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 -40-20 0 2040 6080 temperature (c) relative gain, relative nf (db) nf gain v s = 3 v
7 t7024 4533f?blurf?09/04 figure 7. lna: typical switch-out current versus r switch figure 8. pa (psso20): output power and pae versus supply figure 9. pa (psso20): output power and pae versus ramp voltage 0 4 8 12 16 20 1 10 100 1000 10000 100000 1000000 10000000 r switch ( ? ) i s_o (ma) 0 10 20 30 40 50 2.7 3.1 3.5 3.9 4.3 4.7 supply voltage (v) pout (dbm), pae (%) 100 130 160 190 220 250 i s_tx (ma) pae pout i_s_tx f = 2.4 ghz v ramp = 1.75 v p inpa = 0 dbm -50 -30 -10 10 30 50 1.21.41.61.82.0 v ramp (v) pout (dbm), pae (%) 0 50 100 150 200 250 i s_tx (ma) pae pout i_s_tx f = 2.4 ghz v s = 3 v p inpa = 0 dbm
8 t7024 4533f?blurf?09/04 figure 10. pa (psso20): output power and pae versus input power figure 11. pa (psso20): output power and pae versus frequency figure 12. pa (qfn20): output power and pae versus supply voltage -10 0 10 20 30 40 -40 -30 -20 -10 0 10 input power (dbm) pout (dbm), pae (%), gp (db) 0 50 100 150 200 250 pae pout i_s_tx v s = 3 v f = 2.4 ghz v ramp = 1.75 v pi npa = 0 dbm gain i s_tx (ma) 0 10 20 30 40 50 2400 2420 2440 2460 2480 2500 frequency (mhz) pout (dbm), pae (%) 0 50 100 150 200 250 i s_tx (ma) pae pout i_s_tx v s = 3 v v ramp = 1.7 v p inpa = 0 dbm 0 10 20 30 40 50 2.7 3.1 3.5 3.9 4.3 4.7 supply voltage (v) pout (dbm), pae (%) 100 130 160 190 220 250 i s_tx (ma) pae pout i_s_tx f = 2.4 ghz v ramp = 1.8 v p inpa = 0 dbm
9 t7024 4533f?blurf?09/04 figure 13. pa (qfn20) output power and pae versus ramp voltage figure 14. pa (qfn20): output power and pae versus input power figure 15. pa (qfn20): output power and pae versus frequency -50 -30 -10 10 30 50 1.2 1.4 1.6 1.8 2.0 v ramp (v) pout (dbm), pae (%) 0 50 100 150 200 250 i s_tx (ma) pae pout i_s_tx f = 2.4 ghz v s = 3 v p inpa = 0 dbm -10 0 10 20 30 40 50 -40 -30 -20 -10 0 10 input power (dbm) pout (dbm), pae (%), gp (db) 0 50 100 150 200 250 300 i s_tx (ma) pae pout i_s_tx v s = 3 v f = 2.4 ghz v ramp = 1.8 v p inpa = 0 dbm gain 0 10 20 30 40 50 2400 2420 2440 2460 2480 2500 frequency (mhz) pout (dbm), pae (%) 0 50 100 150 200 250 i s_tx (ma) pae pout i_s_tx v s = 3 v v ramp = 1.8 v p inpa = 0 dbm
10 t7024 4533f?blurf?09/04 figure 16. lna: supply current versus temperature figure 17. pa (psso20): supply current versus i ramp and temperature figure 18. pa (psso20, qfn20): p out versus v ramp and temperature 6.0 6.2 6.4 6.6 6.8 7.0 7.2 7.4 7.6 7.8 8.0 -40-20 0 20406080 temperature (c) supply current (ma) 0 20 40 60 80 100 120 140 160 180 200 0.1 1.0 10.0 100.0 1000.0 i ramp ( a) supply current (ma) -40c 80c 40c 0c -20 -10 0 10 20 30 1.0 1.2 1.4 1.6 1.8 v ramp (v) pout (dbm) -40c 5 80 25 -15 f = 2.4 ghz v s = 3 v p in = 0 dbm
11 t7024 4533f?blurf?09/04 figure 19. (psso20, qfn20): lna gain (db) versus rx_on (v) input/output circuits figure 20. input circuit pa_in/v1_pa figure 21. input circuit ramp/v1_pa -25.0 -20.0 -15.0 -10.0 -5.0 0.0 5.0 10.0 15.0 20.0 1.01.52.02.53.0 rx_on (v) gain (db) v s = 3 v pa_in v1_pa gnd v1_pa ramp
12 t7024 4533f?blurf?09/04 figure 22. input circuit v2_pa figure 23. input/output circuit v3_pa_out figure 24. input circuit switch_out/r_switch v2_pa gnd v3_pa_out gnd v1_pa gnd switch_out r_switch
13 t7024 4533f?blurf?09/04 figure 25. input circuit lna_in/vs_lna figure 26. input circuit pu/rx_on figure 27. output circuit lna_out vs_lna gnd lna_in vs_lna lna_in / pu vs_lna gnd lna_out
14 t7024 4533f?blurf?09/04 figure 28. typical application t7024 (psso20 package) blocking capacitors depending on application pin-diode replaced by led on application-board r1 is selected with dil-switch 1 2 3 4 5 6 7 8 9 1 0 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 pu rx on 3.9p 3.9nh lna out pa in v1_pa v2_pa 3p3 pa ramp 15nh vs_lna 1.8p lna in switch out r1 5.6nh v3_pa 0p8 pa out harm. termination t7024 1p5
15 t7024 4533f?blurf?09/04 figure 29. typical application t7024 (qfn20 package) 20 19 18 17 16 6 7 8 9 10 1 2 3 4 5 15 14 13 12 11 t7024 3p3 v2_pa 1p 2.2p rx on pu switch out 1.8p lna in vs_lna 18nh v3_pa 0p8 2p2 pa out pa ramp r1 var v1_pa pa in lna out harm. termination blocking capacitors depending on application pin-diode replaced by led on application-board r1 is selected with dil-switch
16 t7024 4533f?blurf?09/04 package information ordering information extended type number package remarks moq t7024-trs psso20 tube 830 pcs. t7024-trq psso20 taped and reeled 4000 pcs. t7024-pgp qfn20 taped and reeled 1500 pcs. t7024-pgq qfn20 taped and reeled 6000 pcs. T7024-PGPM qfn20 taped and reeled pb free, halogen free 1500 pcs. t7024-pgqm qfn20 taped and reeled pb free, halogen free 6000 pcs. demoboard-t7024-pg qfn20 evaluation board qfn 1 demoboard-t7024-tr psso20 evaluation board psso 1
17 t7024 4533f?blurf?09/04
18 t7024 4533f?blurf?09/04 package information pb free
19 t7024 4533f?blurf?09/04 recommended pcb land pattern figure 30. recommended pcb land pattern a c e f d b table 1. recommended pcb land pattern signs sign description size a distance of vias 1.6 mm b size of slug pattern 3.1 mm c distance slug to pins 0.33 mm d diameter of vias 1 mm e width of pin pattern 0.3 mm f distance of pin pattern 0.33 mm
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